1. Field of the Invention
The present invention relates to semiconductor structures and methods of forming semiconductor structures, and more particularly to stacked structures and methods of fabricating stacked structures.
2. Description of the Related Art
With advances associated with electronic products, semiconductor technology has been widely applied in manufacturing memories, central processing units (CPUs), liquid crystal displays (LCDs), light emission diodes (LEDs), laser diodes and other devices or chip sets. In order to achieve high-integration and high-speed goals, dimensions of semiconductor integrated circuits continue to shrink. Various materials and techniques have been proposed to achieve these integration and speed goals and to overcome manufacturing obstacles associated therewith. In order to achieve these goals, a stacked structure including multiple substrates has been proposed to enhance operational speed of circuits.
FIG. 1 is a cross-sectional view of a prior art stacked structure.
A stacked structure 100 includes dies 120, 130 and 140 sequentially mounted over a substrate 110, which includes bump structures 105. Generally, dies 120, 130 and 140 with different circuits provide different functionalities. Thus, dimensions of dies 120, 130 and 140 may be different from each other. The die 120 is coupled to the substrate 110 by bump structures 115. An underfill layer 117 is introduced between the die 120 and substrate 110. The die 120 includes conductive structures 123 formed therethrough. Also, the die 130 includes conductive structures 133 formed therethrough. The dies 120 and 130 are coupled to each other by bonding pads 125 between the dies 120 and 130. The die 140 includes conductive structures 143 formed therethrough. The die 140 is coupled to the die 130 by the bonding pads 135.
Before being joined together, the dies 120, 130 and 140 are subjected to electrical tests for identifying inoperative dies. If the dies 120, 130 and 140 pass these electrical performance tests, they are mounted over the substrate 100. Otherwise, the dies will be discarded. Each of the dies 120, 130 and 140 includes an active region (not shown) including transistors, diodes and circuits formed over surfaces 121, 131 and 141, respectively. The operation of these active regions generates heat, for example, at locations “a,” “b” and/or “c” on the surfaces 121, 131 and 141 of the dies 120, 130 and 140, respectively. In some situations, heat created at these locations can be dissipated by the surfaces 122, 132 and/or 142. If heat cannot be dissipated, the accumulated heat at the active regions may cause the failure of the dies 120, 130 and 140 in the stacked structure, even though each of the dies 120, 130 and 140 passed the requisite electrical tests before mounting.
Further, electrical signals generated near to the location “a” must be transmitted by a metal pattern (not shown) formed on the surface 121 of the die 120 through the conductive structures 123, 125, 133 and 135 to the die 140. The metal pattern used to transmitted signals is complex. This complicated metal pattern may increase parasitic capacitances between neighboring metal lines of the metal pattern. These parasitic capacitances may adversely affect electrical performance of the stacked structure.
From the foregoing, improved stacked structures and methods of forming stacked structures are desired.